#ifdef ARCTIC
/**
 @file sys_at_queue_enq.c

 @date 2021-8-13

 @version v1.0

 The file contains AT QoS queue schedule APIs of sys layer
*/

/***************************************************************
 *
 * Header Files
 *
 ***************************************************************/
#include "sal.h"
#include "ctc_error.h"
#include "ctc_debug.h"
#include "sys_usw_common.h"
#include "sys_usw_chip.h"
#include "sys_usw_qos.h"
#include "sys_at_qos.h"
#include "drv_api.h"

#define __SCHEDULE__

STATIC int32
_sys_at_qos_get_chan_credit_unit(uint8 speed, uint8 is_pps, uint16* credit_unit)
{
    uint16 credit_unit_bps = 0;
    uint16 credit_unit_pps = 0;

    /*
        unit: speed * 10 ^ 9 / 8/(1.35 * 10 ^ 9/52(channel num)) * 4 (mult length adjust)
        200G:  200*1000000000/8/(1.35*1000000000/52) * 4
        speed > 100G, credit unit equals to 100G
    */
    CTC_PTR_VALID_CHECK(credit_unit);
    CTC_MAX_VALUE_CHECK(speed, CTC_PORT_SPEED_MAX - 1);

    switch (speed)
    {
        case CTC_PORT_SPEED_1G:
            credit_unit_bps = 20;
            credit_unit_pps = 1;
            break;
        case CTC_PORT_SPEED_100M:
            credit_unit_bps = 2;
            credit_unit_pps = 1;
            break;
        case CTC_PORT_SPEED_10M:
            credit_unit_bps = 1;
            credit_unit_pps = 1;
            break;
        case CTC_PORT_SPEED_2G5:
            credit_unit_bps = 50;
            credit_unit_pps = 2;
            break;
        case CTC_PORT_SPEED_10G:
            credit_unit_bps = 200;
            credit_unit_pps = 72;
            break;
        case CTC_PORT_SPEED_20G:
            credit_unit_bps = 400;
            credit_unit_pps = 144;
            break;
        case CTC_PORT_SPEED_40G:
            credit_unit_bps = 800;
            credit_unit_pps = 288;
            break;
        case CTC_PORT_SPEED_100G:
            credit_unit_bps = 2000;
            credit_unit_pps = 720;
            break;
        case CTC_PORT_SPEED_5G:
            credit_unit_bps = 100;
            credit_unit_pps = 3;
            break;
        case CTC_PORT_SPEED_25G:
            credit_unit_bps = 500;
            credit_unit_pps = 180;
            break;
        case CTC_PORT_SPEED_50G:
            credit_unit_bps = 1000;
            credit_unit_pps = 360;
            break;
        case CTC_PORT_SPEED_200G:
            credit_unit_bps = 2000;
            credit_unit_pps = 720;
            break;
        case CTC_PORT_SPEED_400G:
            credit_unit_bps = 2000;
            credit_unit_pps = 720;
            break;
        case CTC_PORT_SPEED_800G:
            credit_unit_bps = 2000;
            credit_unit_pps = 720;
            break;
        default:
            return CTC_E_NOT_SUPPORT;
    }

    *credit_unit = is_pps ? credit_unit_pps : credit_unit_bps;

    return CTC_E_NONE;
}
STATIC int32
_sys_at_qos_get_chan_credit_thrd(uint8 speed, uint8 is_pps, uint16* credit_thrd, uint8* high_thrd_multiple)
{
    uint16 credit_thrd_bps = 0;
    uint16 credit_thrd_pps = 0;
    uint8  thrd_multiple = 1;

    /*
        unit: speed * 10 ^ 9 / 8/(1.35 * 10 ^ 9/(52(channel num) + 64 cycell delay))
        200G:  200*1000000000/8/(1.35*1000000000/(52 + 64))
    */
    CTC_PTR_VALID_CHECK(credit_thrd);
    CTC_MAX_VALUE_CHECK(speed, CTC_PORT_SPEED_MAX - 1);

    switch (speed)
    {
        case CTC_PORT_SPEED_1G:
            credit_thrd_bps = 13;
            credit_thrd_pps = 50;
            thrd_multiple = 2;
            break;
        case CTC_PORT_SPEED_100M:
            credit_thrd_bps = 2;
            credit_thrd_pps = 50;
            thrd_multiple = 2;
            break;
        case CTC_PORT_SPEED_10M:
            credit_thrd_bps = 1;
            credit_thrd_pps = 50;
            thrd_multiple = 2;
            break;
        case CTC_PORT_SPEED_2G5:
            credit_thrd_bps = 30;
            credit_thrd_pps = 50;
            thrd_multiple = 2;
            break;
        case CTC_PORT_SPEED_10G:
            credit_thrd_bps = 150;
            credit_thrd_pps = 200;
            thrd_multiple = 2;
            break;
        case CTC_PORT_SPEED_20G:
            credit_thrd_bps = 300;
            credit_thrd_pps = 400;
            thrd_multiple = 2;
            break;
        case CTC_PORT_SPEED_40G:
            credit_thrd_bps = 600;
            credit_thrd_pps = 800;
            thrd_multiple = 2;
            break;
        case CTC_PORT_SPEED_100G:
            credit_thrd_bps = 1500;
            credit_thrd_pps = 2000;
            break;
        case CTC_PORT_SPEED_5G:
            credit_thrd_bps = 75;
            credit_thrd_pps = 100;
            thrd_multiple = 2;
            break;
        case CTC_PORT_SPEED_25G:
            credit_thrd_bps = 375;
            credit_thrd_pps = 500;
            thrd_multiple = 2;
            break;
        case CTC_PORT_SPEED_50G:
            credit_thrd_bps = 750;
            credit_thrd_pps = 1000;
            break;
        case CTC_PORT_SPEED_200G:
            credit_thrd_bps = 3000;
            credit_thrd_pps = 4000;
            break;
        case CTC_PORT_SPEED_400G:
            credit_thrd_bps = 6000;
            credit_thrd_pps = 8000;
            break;
        case CTC_PORT_SPEED_800G:
            credit_thrd_bps = 12000;
            credit_thrd_pps = 16000;
            break;
        default:
            return CTC_E_NOT_SUPPORT;
    }

    *credit_thrd = is_pps ? credit_thrd_pps : credit_thrd_bps;
    *high_thrd_multiple = is_pps ? 1 : thrd_multiple;

    return CTC_E_NONE;
}

int32
sys_at_sch_set_net_chan_credit(uint8 lchip, sys_port_info_t* p_port_info, uint8 is_pps)
{
    uint32 cmd = 0;
    uint16 credit_unit = 0;
    uint16 low_credit_thrd = 0;
    uint8  pp_chan = 0;
    uint8 high_thrd_multiple = 1;
    ds_t ds;

    pp_chan = SYS_AT_QOS_ENCOD_PP_CHAN(p_port_info->sub_chan_id, p_port_info->dp_id);

    if ((SYS_DMPS_NETWORK_PORT == p_port_info->port_type)
        || (SYS_DMPS_CPUMAC_NETWORK_PORT == p_port_info->port_type)
        || (SYS_DMPS_MISC_OTHER_PORT == p_port_info->port_type))
    {
        CTC_ERROR_RETURN(_sys_at_qos_get_chan_credit_unit(p_port_info->speed_mode, is_pps, &credit_unit));
        CTC_ERROR_RETURN(_sys_at_qos_get_chan_credit_thrd(p_port_info->speed_mode, is_pps, &low_credit_thrd, &high_thrd_multiple));
    }
    else
    {
        CTC_ERROR_RETURN(_sys_at_qos_get_chan_credit_unit(CTC_PORT_SPEED_800G, is_pps, &credit_unit));
        CTC_ERROR_RETURN(_sys_at_qos_get_chan_credit_thrd(CTC_PORT_SPEED_800G, is_pps, &low_credit_thrd, &high_thrd_multiple));
    }

    /*credit unit*/
    sal_memset(&ds, 0, sizeof(ds));
    SetDsQMgrCreditUnit(V, creditUnit_f, &ds, credit_unit);
    cmd = DRV_IOW(DsQMgrCreditUnit_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, pp_chan, DRV_CMD_PP_EN(cmd), &ds));
    cmd = DRV_IOW(DsQMgrRdCreditUnit_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, pp_chan, DRV_CMD_PP_EN(cmd), &ds));

    /*credit low thrd*/
    cmd = DRV_IOR(DsQMgrQueCreditLowConfig_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, pp_chan, DRV_CMD_PP_EN(cmd), &ds));
    SetDsQMgrQueCreditLowConfig(V, creditThrd_f, &ds, low_credit_thrd * 2);
    cmd = DRV_IOW(DsQMgrQueCreditLowConfig_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, pp_chan, DRV_CMD_PP_EN(cmd), &ds));

    /*credit mid thrd*/
    sal_memset(&ds, 0, sizeof(ds));
    SetDsQMgrQueCreditMidConfig(V, creditThrd_f, &ds, low_credit_thrd * 8);
    cmd = DRV_IOW(DsQMgrQueCreditMidConfig_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, pp_chan, DRV_CMD_PP_EN(cmd), &ds));

    /*credit high thrd*/
    sal_memset(&ds, 0, sizeof(ds));
    SetDsQMgrQueCreditHighConfig(V, creditThrd_f, &ds, low_credit_thrd * high_thrd_multiple * 100);
    cmd = DRV_IOW(DsQMgrQueCreditHighConfig_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, pp_chan, DRV_CMD_PP_EN(cmd), &ds));

    return CTC_E_NONE;
}

int32
sys_at_sch_set_ecpu_chan_credit(uint8 lchip, uint8 is_pps)
{
    uint8 index = 0;
    sys_port_info_t port_info;

    sal_memset(&port_info, 0, sizeof(sys_port_info_t));
    port_info.dp_id = 0;
    port_info.port_type = SYS_DMPS_MISC_OTHER_PORT;
    port_info.speed_mode = CTC_PORT_SPEED_50G;
    port_info.sub_chan_id = SYS_DMPS_MISC_SUB_CHAN;
    /*eunit channel*/
    for (index=0; index < MCHIP_CAP(SYS_CAP_CPU_REASON_GRP_NUM_EUNIT); index++)
    {
        if (SYS_VCHIP_DUAL_CORE_MODE(lchip) && index >= (MCHIP_CAP(SYS_CAP_CPU_REASON_GRP_NUM_EUNIT) / drv_vchip_get_core_num(lchip)))
        {
            port_info.pp_id = 1 + index - (MCHIP_CAP(SYS_CAP_CPU_REASON_GRP_NUM_EUNIT) / drv_vchip_get_core_num(lchip)) + (SYS_PP_NUM(lchip) / drv_vchip_get_core_num(lchip));
            /*core0 pp1 pp2 & core1 pp1 pp2 dp 0 sub_channel 24 for eunit*/
        }
        else
        {
            port_info.pp_id = 1 + index; /*core0 pp1 pp2 dp 0 sub_channel 24 for eunit*/
        }
        CTC_ERROR_RETURN(sys_at_sch_set_wrr_en(lchip, &port_info, is_pps));
    }

    return CTC_E_NONE;
}

int32
sys_at_sch_set_dma_chan_credit(uint8 lchip, uint8 is_pps)
{
    uint32 cmd = 0;
    uint16 credit_unit = 0;
    uint16 low_credit_thrd = 0;
    uint8 high_thrd_multiple = 1;
    ds_t  ds;

    CTC_ERROR_RETURN(_sys_at_qos_get_chan_credit_unit(CTC_PORT_SPEED_1G, is_pps, &credit_unit));
    CTC_ERROR_RETURN(_sys_at_qos_get_chan_credit_thrd(CTC_PORT_SPEED_1G, is_pps, &low_credit_thrd, &high_thrd_multiple));

    SetQMgrDmaCreditUnitCtl(V, creditUnit_f, &ds, credit_unit);
    cmd = DRV_IOW(QMgrDmaCreditUnitCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    cmd = DRV_IOW(QMgrRdDmaCreditUnitCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

    cmd = DRV_IOR(QMgrDmaQueCreditConfig_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    SetQMgrDmaQueCreditConfig(V, creditLowThrd_f, &ds, low_credit_thrd);
    SetQMgrDmaQueCreditConfig(V, creditMidThrd_f, &ds, low_credit_thrd * 8);
    SetQMgrDmaQueCreditConfig(V, creditHighThrd_f, &ds, low_credit_thrd * 100);
    cmd = DRV_IOW(QMgrDmaQueCreditConfig_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

    return CTC_E_NONE;
}

int32
sys_at_sch_set_wrr_en(uint8 lchip, sys_port_info_t* p_port_info, uint32 enable)
{
    uint8 pp_chan = 0;
    uint32 cmd = 0;
    uint32 field_val[3] = {0};
    QMgrGrpPpsModeCtlUc_m qmgr_ctl_uc;
    QMgrGrpPpsModeCtlMc_m qmgr_ctl_mc;
    QMgrSchModeCtl_m sch_mode_ctl;

    SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,  "enable = %d\n", enable);

    pp_chan = SYS_AT_QOS_ENCOD_PP_CHAN(p_port_info->sub_chan_id, p_port_info->dp_id);
    SYS_QOS_LCHIP_CONVERT(lchip, p_port_info->pp_id);

    /*switch wrr mode, need flush chan credit*/
    CTC_ERROR_RETURN(sys_at_sch_set_net_chan_credit(lchip, p_port_info, enable));

    cmd = DRV_IOR(QMgrGrpPpsModeCtlUc_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, DRV_CMD_PP_EN(cmd), &qmgr_ctl_uc));
    GetQMgrGrpPpsModeCtlUc(A, ppsMode_f, &qmgr_ctl_uc, field_val);
    enable ? CTC_BMP_SET(field_val, pp_chan) : CTC_BMP_UNSET(field_val, pp_chan);
    SetQMgrGrpPpsModeCtlUc(A, ppsMode_f, &qmgr_ctl_uc, field_val);
    cmd = DRV_IOW(QMgrGrpPpsModeCtlUc_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, DRV_CMD_PP_EN(cmd), &qmgr_ctl_uc));

    cmd = DRV_IOR(QMgrGrpPpsModeCtlMc_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, DRV_CMD_PP_EN(cmd), &qmgr_ctl_mc));
    GetQMgrGrpPpsModeCtlMc(A, ppsMode_f, &qmgr_ctl_mc, field_val);
    enable ? CTC_BMP_SET(field_val, pp_chan) : CTC_BMP_UNSET(field_val, pp_chan);
    SetQMgrGrpPpsModeCtlMc(A, ppsMode_f, &qmgr_ctl_mc, field_val);
    cmd = DRV_IOW(QMgrGrpPpsModeCtlMc_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, DRV_CMD_PP_EN(cmd), &qmgr_ctl_mc));

    cmd = DRV_IOR(QMgrSchModeCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, DRV_CMD_PP_EN(cmd), &sch_mode_ctl));
    GetQMgrSchModeCtl(A, schPpsModeMc_f, &sch_mode_ctl, field_val);
    enable ? CTC_BMP_SET(field_val, pp_chan) : CTC_BMP_UNSET(field_val, pp_chan);
    SetQMgrSchModeCtl(A, schPpsModeMc_f, &sch_mode_ctl, field_val);
    SetQMgrSchModeCtl(A, schPpsModeUc_f, &sch_mode_ctl, field_val);
    cmd = DRV_IOW(QMgrSchModeCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, DRV_CMD_PP_EN(cmd), &sch_mode_ctl));

    return CTC_E_NONE;
}

int32
sys_at_sch_get_wrr_en(uint8 lchip, sys_port_info_t* p_port_info, uint32* enable)
{
    uint8 pp_chan = 0;
    uint32 cmd = 0;
    uint32 field_val[2] = {0};
    QMgrGrpPpsModeCtlUc_m qmgr_ctl_uc;

    SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);

    pp_chan = SYS_AT_QOS_ENCOD_PP_CHAN(p_port_info->sub_chan_id, p_port_info->dp_id);
    SYS_QOS_LCHIP_CONVERT(lchip, p_port_info->pp_id);

    cmd = DRV_IOR(QMgrGrpPpsModeCtlUc_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, DRV_CMD_PP_EN(cmd), &qmgr_ctl_uc));
    GetQMgrGrpPpsModeCtlUc(A, ppsMode_f, &qmgr_ctl_uc, field_val);
    *enable = CTC_BMP_ISSET(field_val, pp_chan) ? 1 : 0;

    return CTC_E_NONE;
}

int32
sys_at_sch_wrr_en(uint8 lchip, uint32 gport, uint32* enable, uint8 is_set)
{
    uint16 lport = 0;
    sys_port_info_t port_info = {0};
    CTC_PTR_VALID_CHECK(enable);

    SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,  "gport = %d\n", gport);

    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);
    if (!SYS_GPORT_IS_NETWORK_PORT(gport))
    {
        return CTC_E_INVALID_PORT;
    }
    CTC_ERROR_RETURN(sys_usw_port_api_get_com_info(lchip, lport, 0, &port_info));

    if (is_set)
    {
        CTC_ERROR_RETURN(sys_at_sch_set_wrr_en(lchip, &port_info, *enable));
    }
    else
    {
        CTC_ERROR_RETURN(sys_at_sch_get_wrr_en(lchip, &port_info, enable));
    }

    return CTC_E_NONE;
}

STATIC int32
_sys_at_sch_set_queue_sched(uint8 lchip, sys_queue_node_t* p_queue_node, uint8 type, uint8 queue_offset, uint8 exceed_class, uint16 exceed_weight)
{
    uint32 cmd           = 0;
    uint32 field_val     = 0;
    uint8  group_id      = 0;
    uint8  step          = 0;
    uint8  pp_chan       = 0;
    ds_t   ds;

    SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);

    if (SYS_QUEUE_TYPE_NORMAL == p_queue_node->type || SYS_QUEUE_TYPE_EUNIT == p_queue_node->type)
    {
        pp_chan = SYS_AT_QOS_ENCOD_PP_CHAN(p_queue_node->sub_chan, p_queue_node->dp_id);
        group_id = pp_chan;
    }
    else if (SYS_QUEUE_TYPE_EXCP == p_queue_node->type || SYS_QUEUE_TYPE_EXCP_UC == p_queue_node->type)
    {
        SYS_AT_GROUP_ID(group_id, p_queue_node);
        queue_offset = p_queue_node->offset % MCHIP_CAP(SYS_CAP_REASON_GRP_QUEUE_NUM);
    }

    SYS_QOS_LCHIP_CONVERT(lchip, p_queue_node->pp_id);


    switch (type)
    {
    case CTC_QOS_SCHED_CFG_CONFIRM_CLASS:
    case CTC_QOS_SCHED_CFG_CONFIRM_WEIGHT:
        SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Feature not supported \n");
        return CTC_E_NOT_SUPPORT;

    case CTC_QOS_SCHED_CFG_EXCEED_CLASS:
        CTC_MAX_VALUE_CHECK(exceed_class, MCHIP_CAP(SYS_CAP_QOS_SCHED_MAX_QUE_CLASS));
        cmd = DRV_IOR(DsQMgrQueSchMap_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, group_id, DRV_CMD_PP_EN(cmd), &ds));
        field_val = GetDsQMgrQueSchMap(V, nodeSel_f, &ds);
        p_queue_node->class_prio = exceed_class;
        exceed_class ? CTC_BIT_SET(field_val, queue_offset) : CTC_BIT_UNSET(field_val, queue_offset);
        SetDsQMgrQueSchMap(V, nodeSel_f, &ds, field_val);
        cmd = DRV_IOW(DsQMgrQueSchMap_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, group_id, DRV_CMD_PP_EN(cmd), &ds));
        break;

    case CTC_QOS_SCHED_CFG_EXCEED_WEIGHT:
        /*dma queue not support wdrr, only rr*/
        if (SYS_QUEUE_TYPE_NORMAL == p_queue_node->type)
        {
            CTC_MIN_VALUE_CHECK(exceed_weight, 1);
            CTC_MAX_VALUE_CHECK(exceed_weight, 0x7F);

            step = DsQMgrCosWfqWeight_g_1_weight_f - DsQMgrCosWfqWeight_g_0_weight_f;
            cmd = DRV_IOR(DsQMgrCosWfqWeight_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, group_id, DRV_CMD_PP_EN(cmd), &ds));
            SetDsQMgrCosWfqWeight(V, g_0_weight_f + step * queue_offset, &ds, exceed_weight);
            cmd = DRV_IOW(DsQMgrCosWfqWeight_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, group_id, DRV_CMD_PP_EN(cmd), &ds));
        }
        else
        {
            return CTC_E_INVALID_PARAM;
        }

        break;

    default:
        return CTC_E_INVALID_PARAM;
    }

    return CTC_E_NONE;
}

int32
sys_at_sch_get_queue_sched(uint8 lchip, uint16 queue_id, uint8 queue_offset, uint8* exceed_class, uint16* exceed_weight)
{
    sys_queue_node_t* p_queue_node = NULL;
    ds_t   ds;
    uint32 cmd           = 0;
    uint32 field_val     = 0;
    uint8  group_id      = 0;
    uint8  step          = 0;
    uint8  pp_chan       = 0;

    SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    p_queue_node = ctc_vector_get(p_usw_queue_master[lchip]->queue_vec, queue_id);
    if (NULL == p_queue_node)
    {
        return CTC_E_INVALID_PARAM;
    }
    if (SYS_QUEUE_TYPE_NORMAL == p_queue_node->type || SYS_QUEUE_TYPE_EUNIT == p_queue_node->type)
    {
        pp_chan = SYS_AT_QOS_ENCOD_PP_CHAN(p_queue_node->sub_chan, p_queue_node->dp_id);
        SYS_QOS_LCHIP_CONVERT(lchip, p_queue_node->pp_id);
        group_id = pp_chan;
        step = DsQMgrCosWfqWeight_g_1_weight_f - DsQMgrCosWfqWeight_g_0_weight_f;
        cmd = DRV_IOR(DsQMgrCosWfqWeight_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, group_id, DRV_CMD_PP_EN(cmd), &ds));
        *exceed_weight = GetDsQMgrCosWfqWeight(V, g_0_weight_f + step * queue_offset, &ds);
    }
    else if (SYS_QUEUE_TYPE_EXCP == p_queue_node->type || SYS_QUEUE_TYPE_EXCP_UC == p_queue_node->type)
    {
        SYS_AT_GROUP_ID(group_id, p_queue_node);
        queue_offset = p_queue_node->offset % MCHIP_CAP(SYS_CAP_REASON_GRP_QUEUE_NUM);
    }

    cmd = DRV_IOR(DsQMgrQueSchMap_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, group_id, DRV_CMD_PP_EN(cmd), &ds));
    field_val = GetDsQMgrQueSchMap(V, nodeSel_f, &ds);
    *exceed_class = CTC_IS_BIT_SET(field_val, queue_offset);

    return CTC_E_NONE;
}

STATIC int32
_sys_at_queue_sch_set_queue_sched(uint8 lchip, ctc_qos_sched_queue_t* p_sched)
{
    uint16 queue_id  = 0;
    uint16 offset    = 0;
    sys_queue_node_t* p_sys_queue_node = NULL;

    SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,  "p_sched->cfg_type = %d\n", p_sched->cfg_type);
    SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,  "p_sched->queue.queue_type = %d\n", p_sched->queue.queue_type);
    SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,  "p_sched->queue.queue_id = %d\n", p_sched->queue.queue_id);
    SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,  "p_sched->queue.gport = 0x%x\n", p_sched->queue.gport);
    SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,  "p_sched->queue.service_id = 0x%x\n", p_sched->queue.service_id);
    SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,  "p_sched->exceed_weight = %d\n", p_sched->exceed_weight);
    SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,  "p_sched->exceed_class = %d\n", p_sched->exceed_class);

    CTC_ERROR_RETURN(sys_at_queue_get_queue_id(lchip, &p_sched->queue,
                                                       &queue_id));

    SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "queue_id = %d\n", queue_id);

    p_sys_queue_node = ctc_vector_get(p_usw_queue_master[lchip]->queue_vec, queue_id);
    if (NULL == p_sys_queue_node)
    {
        return CTC_E_INVALID_PARAM;
    }
    offset = p_sys_queue_node->offset;

    return _sys_at_sch_set_queue_sched(lchip, p_sys_queue_node, p_sched->cfg_type,
                                                         offset, p_sched->exceed_class, p_sched->exceed_weight);
}

int32
sys_at_queue_sch_get_queue_sched(uint8 lchip, ctc_qos_sched_queue_t* p_sched)
{
    sys_queue_node_t* p_sys_queue_node = NULL;
    uint16 offset  = 0;
    uint16 queue_id = 0;

    SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    if(p_sched->cfg_type == CTC_QOS_SCHED_CFG_CONFIRM_CLASS || p_sched->cfg_type == CTC_QOS_SCHED_CFG_CONFIRM_WEIGHT)
    {
        SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Feature not supported \n");
        return CTC_E_NOT_SUPPORT;
    }

    CTC_ERROR_RETURN(sys_at_queue_get_queue_id(lchip, &p_sched->queue,
                                               &queue_id));

    SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "queue_id = %d\n", queue_id);

    p_sys_queue_node = ctc_vector_get(p_usw_queue_master[lchip]->queue_vec, queue_id);
    if (NULL == p_sys_queue_node)
    {
        return CTC_E_INVALID_PARAM;
    }

    offset = p_sys_queue_node->offset;
    return sys_at_sch_get_queue_sched(lchip, queue_id, offset,
                                                         &p_sched->exceed_class, &p_sched->exceed_weight);
}

STATIC int32
_sys_at_sch_set_group_sch_mode(uint8 lchip, uint16 group_id, ctc_qos_sched_group_t* p_sched)
{
    DsQMgrGrpConfig_m grp_config;
    uint32 cmd = 0;
    uint8  value = 0;

    CTC_MAX_VALUE_CHECK(p_sched->group_type, 1);
    CTC_MAX_VALUE_CHECK(p_sched->class_priority, 1);
    CTC_MAX_VALUE_CHECK(p_sched->mode, 1);

    cmd = DRV_IOR(DsQMgrGrpConfig_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, group_id, DRV_CMD_PP_EN(cmd), &grp_config));

    if (0 == p_sched->group_type)
    {
        SetDsQMgrGrpConfig(V, schModeNode_f, &grp_config, (CTC_QOS_SCHED_MODE_SP == p_sched->mode) ? 0 : 1);
    }
    else
    {
        value = GetDsQMgrGrpConfig(V, schModeSubNode_f, &grp_config);
        (CTC_QOS_SCHED_MODE_SP == p_sched->mode) ? CTC_BIT_SET(value, p_sched->class_priority) : CTC_BIT_UNSET(value, p_sched->class_priority);
        SetDsQMgrGrpConfig(V, schModeSubNode_f, &grp_config, value);
    }
    cmd = DRV_IOW(DsQMgrGrpConfig_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, group_id, DRV_CMD_PP_EN(cmd), &grp_config));

    return CTC_E_NONE;
}

int32
sys_at_queue_sch_set_group_sched(uint8 lchip, ctc_qos_sched_group_t* p_sched)
{
    sys_queue_node_t* p_queue_node = NULL;
    uint32 weight                  = p_sched->weight;
    uint32 cmd                     = 0;
    uint16 group_id                = 0;
    uint16 queue_id                = 0;
    uint8  pp_chan                 = 0;
    DsQMgrGrpParentSelect_m parent_select;

    SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);

    SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,  "p_sched->cfg_type = %d\n", p_sched->cfg_type);
    SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,  "p_sched->queue.gport = 0x%x\n", p_sched->queue.gport);
    SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,  "p_sched->weight = %d\n", p_sched->weight);

    if(p_sched->cfg_type == CTC_QOS_SCHED_CFG_SUB_GROUP_ID || p_sched->cfg_type == CTC_QOS_SCHED_CFG_SUB_GROUP_WEIGHT)
    {
        return CTC_E_INVALID_PARAM;
    }
    CTC_ERROR_RETURN(sys_at_queue_get_queue_id(lchip, &p_sched->queue,
                                                       &queue_id));

    p_queue_node = ctc_vector_get(p_usw_queue_master[lchip]->queue_vec, queue_id);
    if (NULL == p_queue_node)
    {
        return CTC_E_INVALID_PARAM;
    }

    if (SYS_QUEUE_TYPE_NORMAL == p_queue_node->type || SYS_QUEUE_TYPE_EUNIT == p_queue_node->type)
    {
        if (!((p_sched->cfg_type == CTC_QOS_SCHED_CFG_GROUP_SCH_MODE) || (p_sched->cfg_type == CTC_QOS_SCHED_CFG_CONFIRM_WEIGHT && 1 == p_sched->group_type)))
        {
            return CTC_E_INVALID_PARAM;
        }
        pp_chan = SYS_AT_QOS_ENCOD_PP_CHAN(p_queue_node->sub_chan, p_queue_node->dp_id);
        group_id = pp_chan;
    }
    else if (SYS_QUEUE_TYPE_EXCP == p_queue_node->type || SYS_QUEUE_TYPE_EXCP_UC == p_queue_node->type)
    {
        if(p_sched->cfg_type == CTC_QOS_SCHED_CFG_CONFIRM_CLASS)
        {
            SYS_AT_GROUP_ID(group_id, p_queue_node);
            group_id = group_id - MCHIP_CAP(SYS_CAP_QOS_BASE_QUEUE_GRP_NUM);
        }
        else if(p_sched->cfg_type == CTC_QOS_SCHED_CFG_GROUP_SCH_MODE)
        {
            SYS_AT_GROUP_ID(group_id, p_queue_node);
        }
        else
        {
            return CTC_E_INVALID_PARAM;
        }
    }
    else
    {
        return CTC_E_INVALID_PARAM;
    }
    SYS_QOS_LCHIP_CONVERT(lchip, p_queue_node->pp_id);

    SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "group_id = %d\n", group_id);

    switch (p_sched->cfg_type)
    {
    case CTC_QOS_SCHED_CFG_CONFIRM_CLASS:
    {
        CTC_MAX_VALUE_CHECK(p_sched->class_priority, QOS_SCHED_MAX_CHAN_CLASS);
        cmd = DRV_IOR(DsQMgrGrpParentSelect_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, group_id, DRV_CMD_PP_EN(cmd), &parent_select));
        SetDsQMgrGrpParentSelect(V, parentNode_f, &parent_select, p_sched->class_priority);
        cmd = DRV_IOW(DsQMgrGrpParentSelect_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, group_id, DRV_CMD_PP_EN(cmd), &parent_select));
    }
    break;

    case CTC_QOS_SCHED_CFG_CONFIRM_WEIGHT:
        {
            CTC_MIN_VALUE_CHECK(weight, 1);
            CTC_MAX_VALUE_CHECK(weight, 0x7F);
            CTC_MAX_VALUE_CHECK(p_sched->group_type, 1);

            CTC_MAX_VALUE_CHECK(p_sched->class_priority, 1);
            cmd = DRV_IOW(DsQMgrGrpWfqWeight_t, DsQMgrGrpWfqWeight_node_0_weight_f + p_sched->class_priority);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, group_id, DRV_CMD_PP_EN(cmd), &weight));
        }
        break;
    case CTC_QOS_SCHED_CFG_GROUP_SCH_MODE:
        {
            CTC_ERROR_RETURN(_sys_at_sch_set_group_sch_mode(lchip, group_id, p_sched));
        }
        break;

    default:
        break;
    }

    return CTC_E_NONE;
}

STATIC int32
_sys_at_sch_get_group_sch_mode(uint8 lchip, uint16 group_id, ctc_qos_sched_group_t* p_sched)
{
    DsQMgrGrpConfig_m grp_config;
    uint32 cmd = 0;
    uint8  value = 0;

    CTC_MAX_VALUE_CHECK(p_sched->group_type, 1);
    CTC_MAX_VALUE_CHECK(p_sched->class_priority, 1);

    cmd = DRV_IOR(DsQMgrGrpConfig_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, group_id, DRV_CMD_PP_EN(cmd), &grp_config));

    if (0 == p_sched->group_type)
    {
        value = GetDsQMgrGrpConfig(V, schModeNode_f, &grp_config);
        p_sched->mode = value ? CTC_QOS_SCHED_MODE_WDRR : CTC_QOS_SCHED_MODE_SP;
    }
    else
    {
        value = GetDsQMgrGrpConfig(V, schModeSubNode_f, &grp_config);
        p_sched->mode = CTC_IS_BIT_SET(value, p_sched->class_priority) ? CTC_QOS_SCHED_MODE_SP : CTC_QOS_SCHED_MODE_WDRR;

    }

    return CTC_E_NONE;
}

int32
sys_at_queue_sch_get_group_sched(uint8 lchip, ctc_qos_sched_group_t* p_sched)
{
    sys_queue_node_t* p_queue_node = NULL;
    uint32 weight                  = 0;
    uint32 cmd                     = 0;
    uint16 group_id                = 0;
    uint16 queue_id                = 0;
    uint8  pp_chan                 = 0;
    DsQMgrGrpParentSelect_m parent_select;

    SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);

    SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,  "p_sched->cfg_type = %d\n", p_sched->cfg_type);
    SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,  "p_sched->queue.gport = 0x%x\n", p_sched->queue.gport);
    SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_PARAM,  "p_sched->weight = %d\n", p_sched->weight);

    if(p_sched->cfg_type == CTC_QOS_SCHED_CFG_SUB_GROUP_ID || p_sched->cfg_type == CTC_QOS_SCHED_CFG_SUB_GROUP_WEIGHT)
    {
        return CTC_E_INVALID_PARAM;
    }
    CTC_ERROR_RETURN(sys_at_queue_get_queue_id(lchip, &p_sched->queue,
                                                       &queue_id));

    p_queue_node = ctc_vector_get(p_usw_queue_master[lchip]->queue_vec, queue_id);
    if (NULL == p_queue_node)
    {
        return CTC_E_INVALID_PARAM;
    }

    if (SYS_QUEUE_TYPE_NORMAL == p_queue_node->type || SYS_QUEUE_TYPE_EUNIT == p_queue_node->type)
    {
        if (!((p_sched->cfg_type == CTC_QOS_SCHED_CFG_GROUP_SCH_MODE) || (p_sched->cfg_type == CTC_QOS_SCHED_CFG_CONFIRM_WEIGHT && 1 == p_sched->group_type)))
        {
            return CTC_E_INVALID_PARAM;
        }
        pp_chan = SYS_AT_QOS_ENCOD_PP_CHAN(p_queue_node->sub_chan, p_queue_node->dp_id);
        group_id = pp_chan;
    }
    else if (SYS_QUEUE_TYPE_EXCP == p_queue_node->type || SYS_QUEUE_TYPE_EXCP_UC == p_queue_node->type)
    {
        if(p_sched->cfg_type == CTC_QOS_SCHED_CFG_CONFIRM_CLASS)
        {
            SYS_AT_GROUP_ID(group_id, p_queue_node);
            group_id = group_id - MCHIP_CAP(SYS_CAP_QOS_BASE_QUEUE_GRP_NUM);
        }
        else if(p_sched->cfg_type == CTC_QOS_SCHED_CFG_GROUP_SCH_MODE)
        {
            SYS_AT_GROUP_ID(group_id, p_queue_node);
        }
        else
        {
            return CTC_E_INVALID_PARAM;
        }
    }
    else
    {
        return CTC_E_INVALID_PARAM;
    }
    SYS_QOS_LCHIP_CONVERT(lchip, p_queue_node->pp_id);

    SYS_QOS_QUEUE_DBG_OUT(CTC_DEBUG_LEVEL_INFO, "group_id = %d\n", group_id);

    if(p_sched->cfg_type == CTC_QOS_SCHED_CFG_GROUP_SCH_MODE)
    {
        CTC_ERROR_RETURN(_sys_at_sch_get_group_sch_mode(lchip, group_id, p_sched));
    }
    else if(p_sched->cfg_type == CTC_QOS_SCHED_CFG_CONFIRM_WEIGHT)
    {
        CTC_MAX_VALUE_CHECK(p_sched->class_priority, 1);
        cmd = DRV_IOR(DsQMgrGrpWfqWeight_t, DsQMgrGrpWfqWeight_node_0_weight_f + p_sched->class_priority);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, group_id, DRV_CMD_PP_EN(cmd), &weight));
        p_sched->weight = weight;
    }
    else
    {
        cmd = DRV_IOR(DsQMgrGrpParentSelect_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, group_id, DRV_CMD_PP_EN(cmd), &parent_select));
        p_sched->class_priority = GetDsQMgrGrpParentSelect(V, parentNode_f, &parent_select);
    }

    return CTC_E_NONE;
}


#define ______SYS_QOS_SCH_API______

int32
sys_at_qos_set_glb_wrr_enable(uint8 lchip, uint8 enable)
{
    uint16 lport = 0;
    sys_port_info_t port_info;

    for (lport = 0; lport < MCHIP_CAP(SYS_CAP_PORT_NUM_PER_CHIP); lport++)
    {
        CTC_ERROR_RETURN(sys_usw_port_api_get_com_info(lchip, lport, 0, &port_info));

        if ((SYS_DMPS_NETWORK_PORT == port_info.port_type)||(SYS_DMPS_CPUMAC_NETWORK_PORT == port_info.port_type))
        {
            CTC_ERROR_RETURN(sys_at_sch_set_wrr_en(lchip, &port_info, enable));
        }
    }
    return CTC_E_NONE;
}

int32
sys_at_qos_set_sched(uint8 lchip, ctc_qos_sched_t* p_sched)
{
    switch (p_sched->type)
    {
    case CTC_QOS_SCHED_QUEUE:
        CTC_ERROR_RETURN(_sys_at_queue_sch_set_queue_sched(lchip, &p_sched->sched.queue_sched));
        break;
    case CTC_QOS_SCHED_GROUP:
        CTC_ERROR_RETURN(sys_at_queue_sch_set_group_sched(lchip, &p_sched->sched.group_sched));
        break;
    default:
        return CTC_E_INVALID_PARAM;
    }

    return CTC_E_NONE;
}

int32
sys_at_qos_get_sched(uint8 lchip, ctc_qos_sched_t* p_sched)
{
    switch (p_sched->type)
    {
    case CTC_QOS_SCHED_QUEUE:
        CTC_ERROR_RETURN(sys_at_queue_sch_get_queue_sched(lchip, &p_sched->sched.queue_sched));
        break;

    case CTC_QOS_SCHED_GROUP:
        CTC_ERROR_RETURN(sys_at_queue_sch_get_group_sched(lchip, &p_sched->sched.group_sched));
        break;
    default:
        return CTC_E_INVALID_PARAM;
    }

    return CTC_E_NONE;
}


int32
sys_at_queue_sch_init(uint8 lchip)
{
    uint32 cmd = 0;
    uint32 max_size = 0;
    uint16 index = 0;
    DsQMgrL0WfqWeight_m l0_weight;
    DsQMgrGrpWfqWeight_m grp_weight;
    DsQMgrCosWfqWeight_m cos_weight;
    DsQMgrGrpConfigMc_m grp_cfg_mc;
    DsQMgrGrpConfigUc_m grp_cfg_uc;
    QMgrGrpPpsModeCtlUc_m qmgr_ppsmode_uc;
    QMgrGrpPpsModeCtlMc_m qmgr_ppsmode_mc;
    QMgrSchModeCtl_m sch_mode_ctl;
    ds_t ds;
    uint32 field_val[3] = {0};

    sal_memset(&l0_weight, 0, sizeof(l0_weight));
    sal_memset(&grp_weight, 0, sizeof(grp_weight));
    sal_memset(&cos_weight, 0, sizeof(cos_weight));
    sal_memset(&grp_cfg_mc, 0, sizeof(grp_cfg_mc));
    sal_memset(&grp_cfg_uc, 0, sizeof(grp_cfg_uc));
    sal_memset(&qmgr_ppsmode_uc, 0, sizeof(qmgr_ppsmode_uc));
    sal_memset(&qmgr_ppsmode_mc, 0, sizeof(qmgr_ppsmode_mc));
    sal_memset(&sch_mode_ctl, 0, sizeof(sch_mode_ctl));
    /*config default L0 grp sch weight*/
    SetDsQMgrL0WfqWeight(V, node_0_weight_f, &l0_weight, SYS_WFQ_DEFAULT_WEIGHT);
    SetDsQMgrL0WfqWeight(V, node_1_weight_f, &l0_weight, SYS_WFQ_DEFAULT_WEIGHT);
    SetDsQMgrL0WfqWeight(V, node_2_weight_f, &l0_weight, SYS_WFQ_DEFAULT_WEIGHT);
    SetDsQMgrL0WfqWeight(V, node_3_weight_f, &l0_weight, SYS_WFQ_DEFAULT_WEIGHT);
    cmd = DRV_IOW(DsQMgrL0WfqWeight_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &l0_weight));

    /*config default queue grp sch weight*/
    sys_usw_ftm_query_table_entry_num(lchip, DsQMgrGrpWfqWeight_t, &max_size);
    for (index = 0; index < max_size; index++)
    {
        SetDsQMgrGrpWfqWeight(V, node_0_weight_f + index, &grp_weight, SYS_WFQ_DEFAULT_WEIGHT);
        SetDsQMgrGrpWfqWeight(V, node_1_weight_f + index, &grp_weight, SYS_WFQ_DEFAULT_WEIGHT);
        cmd = DRV_IOW(DsQMgrGrpWfqWeight_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &grp_weight));
    }

    /*config default cos sch weight*/
    sys_usw_ftm_query_table_entry_num(lchip, DsQMgrCosWfqWeight_t, &max_size);
    for (index = 0; index < 12; index++)
    {
        SetDsQMgrCosWfqWeight(V, g_0_weight_f + index, &cos_weight, SYS_WFQ_DEFAULT_WEIGHT);
    }

    for (index = 0; index < max_size; index++)
    {
        cmd = DRV_IOW(DsQMgrCosWfqWeight_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &cos_weight));

        cmd = DRV_IOW(DsQMgrQueWfqWeight_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &cos_weight));
    }

    /*config qread sch rr*/
    sys_usw_ftm_query_table_entry_num(lchip, DsQMgrGrpConfigMc_t, &max_size);
    for (index = 0; index < max_size; index++)
    {
        cmd = DRV_IOR(DsQMgrGrpConfigMc_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &grp_cfg_mc));
        SetDsQMgrGrpConfigMc(V, schMode_f, &grp_cfg_mc, 1);
        cmd = DRV_IOW(DsQMgrGrpConfigMc_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &grp_cfg_mc));
    }

    sys_usw_ftm_query_table_entry_num(lchip, DsQMgrGrpConfigUc_t, &max_size);
    for (index = 0; index < max_size; index++)
    {
        cmd = DRV_IOR(DsQMgrGrpConfigUc_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &grp_cfg_uc));
        SetDsQMgrGrpConfigUc(V, schMode_f, &grp_cfg_uc, 1);
        cmd = DRV_IOW(DsQMgrGrpConfigUc_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &grp_cfg_uc));
    }
    /*init dma group ppsMode*/
    for (index = SYS_AT_NETWORK_GROUP_NUM; index < (SYS_AT_DMA_GROUP_NUM_MC + SYS_AT_NETWORK_GROUP_NUM); index++)
    {
        CTC_BMP_SET(field_val, index);
    }
    SetQMgrGrpPpsModeCtlUc(A, ppsMode_f, &qmgr_ppsmode_uc, field_val);
    cmd = DRV_IOW(QMgrGrpPpsModeCtlUc_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &qmgr_ppsmode_uc));

    SetQMgrGrpPpsModeCtlMc(A, ppsMode_f, &qmgr_ppsmode_mc, field_val);
    cmd = DRV_IOW(QMgrGrpPpsModeCtlMc_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &qmgr_ppsmode_mc));

    SetQMgrSchModeCtl(A, schPpsModeMc_f, &sch_mode_ctl, field_val);
    SetQMgrSchModeCtl(A, schPpsModeUc_f, &sch_mode_ctl, field_val);
    cmd = DRV_IOW(QMgrSchModeCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, DRV_CMD_PP_EN(cmd), &sch_mode_ctl));

    sal_memset(&ds, 0, sizeof(ds));
    SetDsQMgrSchSusThrd(V, cfgSusThrd_f, &ds, 4);
    cmd = DRV_IOW(DsQMgrSchSusThrd_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    SetDsQMgrSchSusThrd(V, cfgSusThrd_f, &ds, 7);
    cmd = DRV_IOW(DsQMgrSchSusThrd_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 1, cmd, &ds));
    SetDsQMgrSchSusThrd(V, cfgSusThrd_f, &ds, 800);
    cmd = DRV_IOW(DsQMgrSchSusThrd_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 7, cmd, &ds));
    for (index = 2; index < 7; index++)
    {
        SetDsQMgrSchSusThrd(V, cfgSusThrd_f, &ds, 1 << (index + 2));
        cmd = DRV_IOW(DsQMgrSchSusThrd_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, index, cmd, &ds));
    }

    CTC_ERROR_RETURN(SYS_CB_REGISTER(lchip, SYS_CB_QOS_WRR_EN, sys_at_sch_wrr_en));
    return CTC_E_NONE;
}

int32
sys_at_queue_sch_deinit(uint8 lchip)
{
    SYS_CB_REGISTER(lchip, SYS_CB_QOS_WRR_EN, NULL);

    return CTC_E_NONE;
}

#endif
